The SPI interface was developed by Motorola. Today it is one of the most popular, due to its high speed and exceptional simplicity, of all those that belong to the sequential type. In addition, the SPI interface is also a communication principle. Essentially, SPI is the data transfer logic (master-slave) between two different devices. Physical properties are paid much less attention, they are implemented, as they say, "according to circumstances", while a lower level protocol is not provided. Each manufacturer can contribute something of their own.
SPI Interface: Description
The logic of such a device is serial data transmission (bitwise). In this case, the installation and reading are separated in time due to a special clock on a special bus (it is called a "clock bus", or "synchronization"). Separation is understood as the fact that the process of installing and reading data occurs on opposite edges of the clock pulse generated on the bus. Thanks to this clearly separated in time alternation of readings and settings, it is possible to use the same register for receiving and transmitting information. It is under this principle that the SPI interface was developed. However, the development of technology does not stand still, today large amounts of memory do not pose any problems, and most devices have separate input and output registers. In a nutshell, we examined how the SPI interface works.
Description of the device
The device that generates clock pulses (control) on the clock bus is the “master” (master). Such a device manages the entire process of data exchange, that is, it determines when to start the exchange, when to finish, how many bits of information to transmit, etc. The second device involved in the exchange is called a “slave”. This device does not affect the clock bus in any way. For full-duplex communication (transmission in both directions at the same time), the SP interface uses four lines:
- MOSI - master output and slave input. This line transfers information from the main device to the receiving device.
- MISO - master input and “slave” output. On this wire, the master receives data from the auxiliary device.
- SCLK - clock bus. On this line, the “master” device generates clock pulses.
- SS - the choice of "slave." Using this wire, the master manages the exchange session.
Levels of logic zero and one are encoded by the voltage on the data bus (MISO and MOSI). The SS signal indicates the end and the beginning of an information exchange session. Most often it is inverse. This means that during the data exchange the “master” device must set a low signal on the SS line, and a high signal at the end of the exchange. The presence of the SS level allows you to organize the transfer of several "slave" devices, using one clock signal and one data bus without additional protocols. However, with such a connection, it is necessary to supply a separate SS line from each receiving device.